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cpldfit:  version J.40                              Xilinx Inc.
                                  Fitter Report
Design Name: controlUnit                         Date:  4-29-2011,  4:08PM
Device Used: XA9572XL-15-VQ64
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
44 /72  ( 61%) 137 /360  ( 38%) 68 /216 ( 31%)   19 /72  ( 26%) 37 /52  ( 71%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           6/18        3/54        6/90       6/13
FB2          14/18       26/54       73/90       4/13
FB3          15/18       27/54       40/90       7/14
FB4           9/18       12/54       18/90       5/12
             -----       -----       -----      -----    
             44/72       68/216     137/360     22/52 

* - Resource is exhausted

** Global Control Resources **

Signal 'clk_i' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   14          14    |  I/O              :    31      46
Output        :   22          22    |  GCK/IO           :     3       3
Bidirectional :    0           0    |  GTS/IO           :     2       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     37          37

** Power Data **

There are 0 macrocells in high performance mode (MCHP).
There are 44 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 22 Outputs **

Signal                                    Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                      Pts   Inps          No.  Type    Use     Mode Rate State
enable_IR                                 1     3     FB1_3   12   I/O     O       LOW  FAST 
enable_data                               1     2     FB1_4   13   I/O     O       LOW  FAST 
enable_acc                                1     2     FB1_6   10   I/O     O       LOW  FAST 
pc_reset                                  1     2     FB1_10  18   I/O     O       LOW  FAST 
reg_file_we                               1     2     FB1_15  19   I/O     O       LOW  FAST 
PC_en                                     1     2     FB1_17  20   I/O     O       LOW  FAST 
proc_state<0>                             19    20    FB2_2   60   I/O     O       LOW  FAST RESET
is_branch                                 2     4     FB2_5   61   I/O     O       LOW  FAST RESET
proc_state<1>                             2     3     FB2_10  1    I/O     O       LOW  FAST 
is_call                                   1     1     FB2_17  7    I/O     O       LOW  FAST 
is_load                                   2     4     FB3_2   22   I/O     O       LOW  FAST RESET
is_misc                                   2     4     FB3_5   24   I/O     O       LOW  FAST RESET
is_ret                                    2     4     FB3_6   34   I/O     O       LOW  FAST RESET
is_reti                                   2     4     FB3_9   27   I/O     O       LOW  FAST RESET
is_shift                                  2     4     FB3_12  40   I/O     O       LOW  FAST RESET
is_store                                  2     4     FB3_14  35   I/O     O       LOW  FAST RESET
proc_state<2>                             2     3     FB3_16  42   I/O     O       LOW  FAST 
int_ack                                   2     2     FB4_2   43   I/O     O       LOW  FAST RESET
is_alu                                    2     4     FB4_5   44   I/O     O       LOW  FAST RESET
is_immediate                              2     4     FB4_6   49   I/O     O       LOW  FAST RESET
is_in                                     2     4     FB4_10  51   I/O     O       LOW  FAST RESET
is_jump                                   2     4     FB4_12  52   I/O     O       LOW  FAST RESET

** 22 Buried Nodes **

Signal                                    Total Total Loc     Pwr  Reg Init
Name                                      Pts   Inps          Mode State
s_out/s_out_SETF                          3     8     FB2_4   LOW  
is_store_aux/is_store_aux_SETF            3     8     FB2_6   LOW  
is_shift_aux/is_shift_aux_SETF            3     8     FB2_7   LOW  
is_mem/is_mem_SETF                        3     8     FB2_8   LOW  
is_load_aux/is_load_aux_SETF              3     8     FB2_9   LOW  
is_in_aux/is_in_aux_SETF                  3     8     FB2_11  LOW  
is_alu_aux/is_alu_aux_SETF                6     8     FB2_12  LOW  
state_FFd2                                12    19    FB2_14  LOW  RESET
state_FFd1                                12    12    FB2_15  LOW  RESET
is_interrupt                              1     2     FB2_18  LOW  
is_wait/is_wait_SETF                      3     13    FB3_7   LOW  
is_stdby/is_stdby_SETF                    3     13    FB3_8   LOW  
is_reti_OBUF/is_reti_OBUF_SETF            3     13    FB3_10  LOW  
is_ret_OBUF/is_ret_OBUF_SETF              3     13    FB3_11  LOW  
is_misc_aux/is_misc_aux_SETF              3     10    FB3_13  LOW  
is_jump_aux/is_jump_aux_SETF              3     10    FB3_15  LOW  
is_branch_aux/is_branch_aux_SETF          3     10    FB3_17  LOW  
is_immediate_OBUF/is_immediate_OBUF_SETF  5     8     FB3_18  LOW  
s_out                                     2     4     FB4_15  LOW  RESET
is_wait                                   2     4     FB4_16  LOW  RESET
is_stdby                                  2     4     FB4_17  LOW  RESET
is_mem                                    2     4     FB4_18  LOW  RESET

** 15 Inputs **

Signal                                    Loc     Pin  Pin     Pin     
Name                                              No.  Type    Use     
instr_ack_i                               FB1_8   11   I/O     I
clk_i                                     FB1_9   15~  GCK/I/O GCK
int_req                                   FB1_11  16   GCK/I/O I
port_ack_i                                FB1_14  17   GCK/I/O I
opcode_comp_in<0>                         FB2_3   58   I/O     I
cod_ext3_in<0>                            FB2_4   59   I/O     I
opcode_comp_in<1>                         FB2_9   64   GSR/I/O I
cod_ext3_in<1>                            FB2_11  2    GTS/I/O I
cod_ext3_in<2>                            FB2_12  4    I/O     I
data_ack_i                                FB2_14  5    GTS/I/O I
opcode_in<1>                              FB3_17  38   I/O     I
opcode_in<0>                              FB4_8   45   I/O     I
opcode_in<3>                              FB4_14  50   I/O     I
opcode_in<2>                              FB4_15  56   I/O     I
clr_i                                     FB4_17  57   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               3/51
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2   8     I/O     
enable_IR             1       0     0   4     FB1_3   12    I/O     O
enable_data           1       0     0   4     FB1_4   13    I/O     O
(unused)              0       0     0   5     FB1_5   9     I/O     
enable_acc            1       0     0   4     FB1_6   10    I/O     O
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   11    I/O     I
(unused)              0       0     0   5     FB1_9   15    GCK/I/O GCK
pc_reset              1       0     0   4     FB1_10  18    I/O     O
(unused)              0       0     0   5     FB1_11  16    GCK/I/O I
(unused)              0       0     0   5     FB1_12  23    I/O     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  17    GCK/I/O I
reg_file_we           1       0     0   4     FB1_15  19    I/O     O
(unused)              0       0     0   5     FB1_16        (b)     
PC_en                 1       0     0   4     FB1_17  20    I/O     O
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: proc_state<0>      2: state_FFd1         3: state_FFd2 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
enable_IR            XXX..................................... 3
enable_data          X.X..................................... 2
enable_acc           X.X..................................... 2
pc_reset             X.X..................................... 2
reg_file_we          XX...................................... 2
PC_en                XX...................................... 2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/5   0     FB2_1         (b)     (b)
proc_state<0>        19      14<-   0   0     FB2_2   60    I/O     O
(unused)              0       0   /\5   0     FB2_3   58    I/O     I
s_out/s_out_SETF      3       0     0   2     FB2_4   59    I/O     I
is_branch             2       0     0   3     FB2_5   61    I/O     O
is_store_aux/is_store_aux_SETF
                      3       0     0   2     FB2_6   62    I/O     (b)
is_shift_aux/is_shift_aux_SETF
                      3       0     0   2     FB2_7         (b)     (b)
is_mem/is_mem_SETF    3       0     0   2     FB2_8   63    I/O     (b)
is_load_aux/is_load_aux_SETF
                      3       0     0   2     FB2_9   64    GSR/I/O I
proc_state<1>         2       0     0   3     FB2_10  1     I/O     O
is_in_aux/is_in_aux_SETF
                      3       0   \/1   1     FB2_11  2     GTS/I/O I
is_alu_aux/is_alu_aux_SETF
                      6       1<-   0   0     FB2_12  4     I/O     I
(unused)              0       0   \/5   0     FB2_13        (b)     (b)
state_FFd2           12       7<-   0   0     FB2_14  5     GTS/I/O I
state_FFd1           12       9<- /\2   0     FB2_15  6     I/O     (b)
(unused)              0       0   /\5   0     FB2_16        (b)     (b)
is_call               1       0   /\4   0     FB2_17  7     I/O     O
is_interrupt          1       0   \/4   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clr_i                             10: is_load           19: opcode_in<2> 
  2: data_ack_i                        11: is_mem            20: opcode_in<3> 
  3: instr_ack_i                       12: is_misc           21: pc_reset 
  4: int_req                           13: is_shift          22: port_ack_i 
  5: is_alu                            14: is_stdby          23: proc_state<0> 
  6: is_branch                         15: is_store          24: s_out 
  7: is_branch_aux/is_branch_aux_SETF  16: is_wait           25: state_FFd1 
  8: is_in                             17: opcode_in<0>      26: state_FFd2 
  9: is_jump                           18: opcode_in<1>     

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
proc_state<0>        XXXXXX.XXXXXXXXX.....XXXXX.............. 20
s_out/s_out_SETF     ................XXXX..XXXX.............. 8
is_branch            ......X.............X.X.X............... 4
is_store_aux/is_store_aux_SETF 
                     ..............X.XXXX..X.XX.............. 8
is_shift_aux/is_shift_aux_SETF 
                     ............X...XXXX..X.XX.............. 8
is_mem/is_mem_SETF   ..........X.....XXXX..X.XX.............. 8
is_load_aux/is_load_aux_SETF 
                     .........X......XXXX..X.XX.............. 8
proc_state<1>        ......................X.XX.............. 3
is_in_aux/is_in_aux_SETF 
                     .......X........XXXX..X.XX.............. 8
is_alu_aux/is_alu_aux_SETF 
                     ....X...........XXXXX.X.X............... 8
state_FFd2           XX.XXX.XXXXXXXXX.....XXXXX.............. 19
state_FFd1           XX.X...X.XX...X......XXXXX.............. 12
is_call              ....................X................... 1
is_interrupt         ......................X..X.............. 2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               27/27
Number of signals used by logic mapping into function block:  27
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
is_load               2       0     0   3     FB3_2   22    I/O     O
(unused)              0       0     0   5     FB3_3   31    I/O     
(unused)              0       0     0   5     FB3_4   32    I/O     
is_misc               2       0     0   3     FB3_5   24    I/O     O
is_ret                2       0     0   3     FB3_6   34    I/O     O
is_wait/is_wait_SETF
                      3       0     0   2     FB3_7         (b)     (b)
is_stdby/is_stdby_SETF
                      3       0     0   2     FB3_8   25    I/O     (b)
is_reti               2       0     0   3     FB3_9   27    I/O     O
is_reti_OBUF/is_reti_OBUF_SETF
                      3       0     0   2     FB3_10  39    I/O     (b)
is_ret_OBUF/is_ret_OBUF_SETF
                      3       0     0   2     FB3_11  33    I/O     (b)
is_shift              2       0     0   3     FB3_12  40    I/O     O
is_misc_aux/is_misc_aux_SETF
                      3       0     0   2     FB3_13        (b)     (b)
is_store              2       0     0   3     FB3_14  35    I/O     O
is_jump_aux/is_jump_aux_SETF
                      3       0     0   2     FB3_15  36    I/O     (b)
proc_state<2>         2       0     0   3     FB3_16  42    I/O     O
is_branch_aux/is_branch_aux_SETF
                      3       0     0   2     FB3_17  38    I/O     I
is_immediate_OBUF/is_immediate_OBUF_SETF
                      5       0     0   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: cod_ext3_in<0>                10: is_ret                          19: opcode_comp_in<1> 
  2: cod_ext3_in<1>                11: is_ret_OBUF/is_ret_OBUF_SETF    20: opcode_in<0> 
  3: cod_ext3_in<2>                12: is_reti                         21: opcode_in<1> 
  4: is_branch                     13: is_reti_OBUF/is_reti_OBUF_SETF  22: opcode_in<2> 
  5: is_immediate                  14: is_shift_aux/is_shift_aux_SETF  23: opcode_in<3> 
  6: is_jump                       15: is_stdby                        24: pc_reset 
  7: is_load_aux/is_load_aux_SETF  16: is_store_aux/is_store_aux_SETF  25: proc_state<0> 
  8: is_misc                       17: is_wait                         26: state_FFd1 
  9: is_misc_aux/is_misc_aux_SETF  18: opcode_comp_in<0>               27: state_FFd2 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
is_load              ......X................XXX.............. 4
is_misc              ........X..............XXX.............. 4
is_ret               ..........X............XXX.............. 4
is_wait/is_wait_SETF 
                     XXX.............XXXXXXX.XXX............. 13
is_stdby/is_stdby_SETF 
                     XXX...........X..XXXXXX.XXX............. 13
is_reti              ............X..........XXX.............. 4
is_reti_OBUF/is_reti_OBUF_SETF 
                     XXX........X.....XXXXXX.XXX............. 13
is_ret_OBUF/is_ret_OBUF_SETF 
                     XXX......X.......XXXXXX.XXX............. 13
is_shift             .............X.........XXX.............. 4
is_misc_aux/is_misc_aux_SETF 
                     .......X.........XXXXXX.XXX............. 10
is_store             ...............X.......XXX.............. 4
is_jump_aux/is_jump_aux_SETF 
                     .....X...........XXXXXX.XXX............. 10
proc_state<2>        .......................XXX.............. 3
is_branch_aux/is_branch_aux_SETF 
                     ...X.............XXXXXX.XXX............. 10
is_immediate_OBUF/is_immediate_OBUF_SETF 
                     ....X..............XXXXXXX.............. 8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               12/42
Number of signals used by logic mapping into function block:  12
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
int_ack               2       0     0   3     FB4_2   43    I/O     O
(unused)              0       0     0   5     FB4_3   46    I/O     
(unused)              0       0     0   5     FB4_4   47    I/O     
is_alu                2       0     0   3     FB4_5   44    I/O     O
is_immediate          2       0     0   3     FB4_6   49    I/O     O
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   45    I/O     I
(unused)              0       0     0   5     FB4_9         (b)     
is_in                 2       0     0   3     FB4_10  51    I/O     O
(unused)              0       0     0   5     FB4_11  48    I/O     
is_jump               2       0     0   3     FB4_12  52    I/O     O
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  50    I/O     I
s_out                 2       0     0   3     FB4_15  56    I/O     I
is_wait               2       0     0   3     FB4_16        (b)     (b)
is_stdby              2       0     0   3     FB4_17  57    I/O     I
is_mem                2       0     0   3     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: is_alu_aux/is_alu_aux_SETF                 5: is_jump_aux/is_jump_aux_SETF   9: pc_reset 
  2: is_immediate_OBUF/is_immediate_OBUF_SETF   6: is_mem/is_mem_SETF            10: proc_state<0> 
  3: is_in_aux/is_in_aux_SETF                   7: is_stdby/is_stdby_SETF        11: s_out/s_out_SETF 
  4: is_interrupt                               8: is_wait/is_wait_SETF          12: state_FFd1 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
int_ack              ...X....X............................... 2
is_alu               X.......XX.X............................ 4
is_immediate         .X......XX.X............................ 4
is_in                ..X.....XX.X............................ 4
is_jump              ....X...XX.X............................ 4
s_out                ........XXXX............................ 4
is_wait              .......XXX.X............................ 4
is_stdby             ......X.XX.X............................ 4
is_mem               .....X..XX.X............................ 4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********










PC_en <= (NOT proc_state(0) AND state_FFd1);


enable_IR <= (NOT proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2);


enable_acc <= (NOT proc_state(0) AND state_FFd2);


enable_data <= (NOT proc_state(0) AND state_FFd2);

FDCPE_int_ack: FDCPE port map (int_ack,'0','0',int_ack_CLR,int_ack_PRE);
int_ack_CLR <= (NOT pc_reset AND NOT is_interrupt);
int_ack_PRE <= (NOT pc_reset AND is_interrupt);

FDCPE_is_alu: FDCPE port map (is_alu,'0','0',is_alu_CLR,is_alu_aux/is_alu_aux_SETF);
is_alu_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_alu_aux/is_alu_aux_SETF);


is_alu_aux/is_alu_aux_SETF <= ((is_in_aux/is_in_aux_SETF.EXP)
	OR (NOT opcode_in(3) AND NOT opcode_in(2) AND proc_state(0) AND 
	NOT pc_reset AND NOT state_FFd1)
	OR (NOT opcode_in(3) AND NOT opcode_in(1) AND proc_state(0) AND 
	NOT pc_reset AND NOT state_FFd1)
	OR (NOT opcode_in(3) AND NOT opcode_in(0) AND proc_state(0) AND 
	NOT pc_reset AND NOT state_FFd1)
	OR (NOT opcode_in(3) AND proc_state(0) AND NOT pc_reset AND 
	is_alu AND NOT state_FFd1)
	OR (opcode_in(2) AND opcode_in(1) AND NOT opcode_in(0) AND 
	proc_state(0) AND NOT pc_reset AND NOT state_FFd1));

FDCPE_is_branch: FDCPE port map (is_branch,'0','0',is_branch_CLR,is_branch_aux/is_branch_aux_SETF);
is_branch_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_branch_aux/is_branch_aux_SETF);


is_branch_aux/is_branch_aux_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_branch AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_branch AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
	NOT opcode_comp_in(1) AND NOT opcode_comp_in(0)));


is_call <= pc_reset;

FDCPE_is_immediate: FDCPE port map (is_immediate,'0','0',is_immediate_CLR,is_immediate_OBUF/is_immediate_OBUF_SETF);
is_immediate_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_immediate_OBUF/is_immediate_OBUF_SETF);


is_immediate_OBUF/is_immediate_OBUF_SETF <= ((NOT opcode_in(3) AND NOT opcode_in(2) AND proc_state(0) AND 
	NOT pc_reset AND NOT state_FFd1)
	OR (NOT opcode_in(3) AND NOT opcode_in(1) AND proc_state(0) AND 
	NOT pc_reset AND NOT state_FFd1)
	OR (NOT opcode_in(3) AND NOT opcode_in(0) AND proc_state(0) AND 
	NOT pc_reset AND NOT state_FFd1)
	OR (NOT opcode_in(3) AND proc_state(0) AND NOT pc_reset AND 
	is_immediate AND NOT state_FFd1)
	OR (opcode_in(2) AND NOT opcode_in(1) AND opcode_in(0) AND 
	proc_state(0) AND NOT pc_reset AND is_immediate AND NOT state_FFd1));

FDCPE_is_in: FDCPE port map (is_in,'0','0',is_in_CLR,is_in_aux/is_in_aux_SETF);
is_in_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_in_aux/is_in_aux_SETF);


is_in_aux/is_in_aux_SETF <= ((opcode_in(3) AND NOT opcode_in(2) AND opcode_in(1) AND 
	NOT opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
	OR (opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_in AND NOT state_FFd1 AND NOT state_FFd2)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_in AND NOT state_FFd1 AND NOT state_FFd2));


is_interrupt <= (proc_state(0) AND state_FFd2);

FDCPE_is_jump: FDCPE port map (is_jump,'0','0',is_jump_CLR,is_jump_aux/is_jump_aux_SETF);
is_jump_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_jump_aux/is_jump_aux_SETF);


is_jump_aux/is_jump_aux_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_jump AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_jump AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
	opcode_comp_in(1) AND NOT opcode_comp_in(0)));

FDCPE_is_load: FDCPE port map (is_load,'0','0',is_load_CLR,is_load_aux/is_load_aux_SETF);
is_load_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_load_aux/is_load_aux_SETF);


is_load_aux/is_load_aux_SETF <= ((opcode_in(3) AND NOT opcode_in(2) AND NOT opcode_in(1) AND 
	NOT opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
	OR (opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_load AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_load AND NOT state_FFd1 AND 
	NOT state_FFd2));

FDCPE_is_mem: FDCPE port map (is_mem,'0','0',is_mem_CLR,is_mem/is_mem_SETF);
is_mem_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_mem/is_mem_SETF);


is_mem/is_mem_SETF <= ((opcode_in(3) AND NOT opcode_in(2) AND proc_state(0) AND 
	NOT state_FFd1 AND NOT state_FFd2)
	OR (opcode_in(3) AND NOT opcode_in(1) AND opcode_in(0) AND 
	proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND is_mem)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
	is_mem));

FDCPE_is_misc: FDCPE port map (is_misc,'0','0',is_misc_CLR,is_misc_aux/is_misc_aux_SETF);
is_misc_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_misc_aux/is_misc_aux_SETF);


is_misc_aux/is_misc_aux_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_misc AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_misc AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
	opcode_comp_in(1) AND opcode_comp_in(0)));

FDCPE_is_ret: FDCPE port map (is_ret,'0','0',is_ret_CLR,is_ret_OBUF/is_ret_OBUF_SETF);
is_ret_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_ret_OBUF/is_ret_OBUF_SETF);


is_ret_OBUF/is_ret_OBUF_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_ret AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_ret AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND NOT cod_ext3_in(2) AND NOT cod_ext3_in(1) AND NOT cod_ext3_in(0) AND 
	proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND opcode_comp_in(1) AND 
	opcode_comp_in(0)));

FDCPE_is_reti: FDCPE port map (is_reti,'0','0',is_reti_CLR,is_reti_OBUF/is_reti_OBUF_SETF);
is_reti_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_reti_OBUF/is_reti_OBUF_SETF);


is_reti_OBUF/is_reti_OBUF_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_reti AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_reti AND NOT state_FFd1 AND 
	NOT state_FFd2)
	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND NOT cod_ext3_in(2) AND NOT cod_ext3_in(1) AND cod_ext3_in(0) AND 
	proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND opcode_comp_in(1) AND 
	opcode_comp_in(0)));

FDCPE_is_shift: FDCPE port map (is_shift,'0','0',is_shift_CLR,is_shift_aux/is_shift_aux_SETF);
is_shift_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_shift_aux/is_shift_aux_SETF);


is_shift_aux/is_shift_aux_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	NOT opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
	OR (opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	proc_state(0) AND is_shift AND NOT state_FFd1 AND NOT state_FFd2)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_shift AND NOT state_FFd1 AND 
	NOT state_FFd2));

FDCPE_is_stdby: FDCPE port map (is_stdby,'0','0',is_stdby_CLR,is_stdby/is_stdby_SETF);
is_stdby_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_stdby/is_stdby_SETF);


is_stdby/is_stdby_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
	is_stdby)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
	is_stdby)
	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND cod_ext3_in(2) AND NOT cod_ext3_in(1) AND cod_ext3_in(0) AND 
	proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND opcode_comp_in(1) AND 
	opcode_comp_in(0)));

FDCPE_is_store: FDCPE port map (is_store,'0','0',is_store_CLR,is_store_aux/is_store_aux_SETF);
is_store_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_store_aux/is_store_aux_SETF);


is_store_aux/is_store_aux_SETF <= ((opcode_in(3) AND NOT opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
	OR (opcode_in(3) AND NOT opcode_in(1) AND opcode_in(0) AND 
	proc_state(0) AND is_store AND NOT state_FFd1 AND NOT state_FFd2)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND is_store AND NOT state_FFd1 AND 
	NOT state_FFd2));

FDCPE_is_wait: FDCPE port map (is_wait,'0','0',is_wait_CLR,is_wait/is_wait_SETF);
is_wait_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT is_wait/is_wait_SETF);


is_wait/is_wait_SETF <= ((opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
	is_wait)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND 
	is_wait)
	OR (opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND cod_ext3_in(2) AND NOT cod_ext3_in(1) AND NOT cod_ext3_in(0) AND 
	proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2 AND opcode_comp_in(1) AND 
	opcode_comp_in(0)));


pc_reset <= (proc_state(0) AND state_FFd2);

FDCPE_proc_state0: FDCPE port map (proc_state(0),proc_state_D(0),clk_i,'0','0');
proc_state_D(0) <= ((EXP6_.EXP)
	OR (EXP7_.EXP)
	OR (int_req AND NOT clr_i AND NOT proc_state(0) AND state_FFd1)
	OR (NOT port_ack_i AND NOT clr_i AND proc_state(0) AND state_FFd1 AND 
	s_out)
	OR (instr_ack_i AND NOT clr_i AND NOT proc_state(0) AND 
	NOT state_FFd1 AND NOT state_FFd2)
	OR (NOT port_ack_i AND NOT data_ack_i AND NOT clr_i AND NOT proc_state(0) AND 
	is_load AND state_FFd2 AND is_mem)
	OR (int_req AND NOT clr_i AND proc_state(0) AND NOT is_alu AND 
	NOT is_shift AND NOT state_FFd1 AND NOT state_FFd2 AND NOT is_mem));


proc_state(1) <= ((proc_state(0) AND state_FFd1)
	OR (NOT proc_state(0) AND state_FFd2));


proc_state(2) <= NOT (((proc_state(0) AND NOT pc_reset)
	OR (NOT pc_reset AND NOT state_FFd1)));


reg_file_we <= (NOT proc_state(0) AND state_FFd1);

FDCPE_s_out: FDCPE port map (s_out,'0','0',s_out_CLR,s_out/s_out_SETF);
s_out_CLR <= (proc_state(0) AND NOT pc_reset AND NOT state_FFd1 AND 
	NOT s_out/s_out_SETF);


s_out/s_out_SETF <= ((opcode_in(3) AND NOT opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
	OR (opcode_in(3) AND opcode_in(2) AND NOT opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND s_out AND NOT state_FFd2)
	OR (NOT opcode_in(3) AND opcode_in(2) AND opcode_in(1) AND 
	opcode_in(0) AND proc_state(0) AND NOT state_FFd1 AND s_out AND NOT state_FFd2));

FDCPE_state_FFd1: FDCPE port map (state_FFd1,state_FFd1_D,clk_i,'0','0');
state_FFd1_D <= ((clr_i)
	OR (EXP9_.EXP)
	OR (proc_state(0) AND NOT state_FFd1)
	OR (NOT proc_state(0) AND NOT state_FFd2));

FTCPE_state_FFd2: FTCPE port map (state_FFd2,state_FFd2_T,clk_i,'0','0');
state_FFd2_T <= ((EXP8_.EXP)
	OR (state_FFd1.EXP)
	OR (clr_i AND NOT state_FFd2)
	OR (NOT proc_state(0) AND NOT state_FFd1 AND NOT state_FFd2)
	OR (NOT int_req AND is_misc AND NOT state_FFd2 AND is_stdby)
	OR (NOT int_req AND is_misc AND NOT state_FFd2 AND is_wait)
	OR (NOT int_req AND NOT is_alu AND NOT is_shift AND NOT state_FFd2 AND 
	NOT is_mem));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XA9572XL-15-VQ64


   -----------------------------------------------  
  /48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \
 | 49                                           32 | 
 | 50                                           31 | 
 | 51                                           30 | 
 | 52                                           29 | 
 | 53                                           28 | 
 | 54                                           27 | 
 | 55                                           26 | 
 | 56              XA9572XL-15-VQ64             25 | 
 | 57                                           24 | 
 | 58                                           23 | 
 | 59                                           22 | 
 | 60                                           21 | 
 | 61                                           20 | 
 | 62                                           19 | 
 | 63                                           18 | 
 | 64                                           17 | 
 \ 1  2  3  4  5  6  7  8  9  10 11 12 13 14 15 16 /
   -----------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 proc_state<1>                    33 KPR                           
  2 cod_ext3_in<1>                   34 is_ret                        
  3 VCC                              35 is_store                      
  4 cod_ext3_in<2>                   36 KPR                           
  5 data_ack_i                       37 VCC                           
  6 KPR                              38 opcode_in<1>                  
  7 is_call                          39 KPR                           
  8 KPR                              40 is_shift                      
  9 KPR                              41 GND                           
 10 enable_acc                       42 proc_state<2>                 
 11 instr_ack_i                      43 int_ack                       
 12 enable_IR                        44 is_alu                        
 13 enable_data                      45 opcode_in<0>                  
 14 GND                              46 KPR                           
 15 clk_i                            47 KPR                           
 16 int_req                          48 KPR                           
 17 port_ack_i                       49 is_immediate                  
 18 pc_reset                         50 opcode_in<3>                  
 19 reg_file_we                      51 is_in                         
 20 PC_en                            52 is_jump                       
 21 GND                              53 TDO                           
 22 is_load                          54 GND                           
 23 KPR                              55 VCC                           
 24 is_misc                          56 opcode_in<2>                  
 25 KPR                              57 clr_i                         
 26 VCC                              58 opcode_comp_in<0>             
 27 is_reti                          59 cod_ext3_in<0>                
 28 TDI                              60 proc_state<0>                 
 29 TMS                              61 is_branch                     
 30 TCK                              62 KPR                           
 31 KPR                              63 KPR                           
 32 KPR                              64 opcode_comp_in<1>             


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xa95*xl-*-*
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : LOW
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25
</pre>
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